A power-scalable variable-length analogue DFT processor for multi-standard wireless transceivers

Since the invention of the mobile phone, a new generation of mobile communication standard has emerged every 10 years. Upgrading the technology of mobile networks in all areas takes few years. Hence, mobile phones should support the previous communication standards as well as the latest standards. Realizing a multi-standard mobile phone by multiple transceivers in parallel is neither a size-efficient nor a cost-efficient solution. Hence, modern mobile phones demand reconfigurable transceivers. It is also essential for mobile phones to consume power efficiently. Hence, the multi-standard transceiver should scale its power consumption to the standard specifications. Many recent communication standards are based on the Orthogonal Frequency-Division Multiplexing (OFDM). In the OFDM based transceivers, digital computation of the Discrete Fourier Transform (DFT) is a power hungry process. Reduction in the hardware cost and power consumption is possible by implementing the DFT processor with analogue circuits. Accordingly, the goal of this work is to design a powerscalable variable-length analogue DFT processor for multi-standard OFDM transceivers. Since the Fast Fourier Transform (FFT) algorithm reduces the computational burden of the DFT, it has been used to reduce the hardware cost and power consumption of the digital DFT processors for years. However, the FFT algorithm was originally designed for discrete-time signal processing. This thesis presents the real-time recursive DFT architecture, which was designed based on the characteristics of the analogue signal processing domain. The optimal architecture for the analogue DFT is achieved by keeping the signal continuous as long as possible. In order to analyse the performance of the proposed architecture, system-level simulations on the real-time recursive DFT processor and the radix-2 FFT processor of length 8 were performed. Results of the system performance analysis indicate that the average dynamic range of the proposed processor is 4.7 dB higher than the FFT processor. In the Monte Carlo analysis, the DFT processors that succeed in meeting the minimum dynamic range requirement (34dB) contribute to the yield. Accordingly, the proposed architecture has a yield of 99.3% while the yield of the FFT processor is 82.8%. The real-time recursive DFT architecture was realized by the four-quadrant transconductance multipliers and the parasitic-insensitive switched-capacitor integrators. The real-time recursive DFT processor was designed in 180 nm CMOS technology. Sensitivity of the realtime recursive DFT processor to device mismatch was analysed using the Pelgrom’s model. Results of device mismatch analysis indicate that the 8-point recursive DFT processor has a yield of 97.5% for the BPSK modulated signal. For the QPSK modulated signal, however, yield of the 8-point recursive DFT processor is 8.9%. Moreover, doubling the transform length reduces the average dynamic range by 3dB. Accordingly, the 16-point recursive DFT processor has a yield of 43.4% for the BPSK modulated signal. Power consumption of the recursive DFT processor is about 1/6 of the power consumption of a previous analogue FFT processor. This thesis provided a proof-of-concept for the power-scalable variable-length analogue DFT processor. Previously, changing the transform length and scaling the power could only be performed by digital FFT processors. By using the real-time recursive DFT processor, the analogue decimation filter is eliminated. Thus, further reduction in the hardware cost and power consumption of the multi-standard transceiver is achieved.